Field effect transistors (FETs) and doped polysilicon resistors are common elements in solid state circuits. Gate conductors are formed by the deposition of crystalline polysilicon which is subsequently doped and, in many instances, must have a predetermined electrical resistance. Furthermore, it is important that polysilicon electrical depletion adjacent to an interface with dielectric be minimized in order to improve transistor performance.
U.S. Pat. No. 6,017,810, to Furukawa et al., titled “Process for Fabricating Field Effect Transistor with a Self-Aligned Gate to Device Isolation”, suggests a method for forming a gate conductor from an N+ or P+ type doped polycrystalline silicon on an insulating layer, but does not teach variation of crystal grain size in controlled manner.
U.S. Pat. No. 5,766,989, to Maegawa et al., titled “Method for Forming Polycrystalline Thin Film and Method for Fabricating Thin Film Transistor”, suggests a method of forming a polysilicon semiconductor thin film, which, in part, contains microcrystals that serve as crystal nuclei for polycrystallization on an insulating substrate. The film is polycrystallized by laser annealing to generate crystals all of substantially the same size. This reference discusses prior art in which excimer laser radiation is employed to generate polycrystalline layers having crystals of different size where the variation occurs laterally, i.e., in a direction perpendicular to a direction of the thickness of the polysilicon.
U.S. Pat. No. 5,346,850, to Kaschmitter et al., titled “Crystallization and Doping of Silicon on Low Temperature Plastic”, suggests the use of short-pulsed high energy processing of an amorphous silicon layer to crystallize the same.
U.S. Pat. No. 5,164,338, to Graeger et al., titled “Method of Manufacturing a Polycrystalline Semiconductor Resistance Layer of Silicon on a Silicon body and Silicon Pressure Sensor Having Such a Resistance Layer,” suggests a method of manufacturing a polycrystalline semiconductor resistance layer over an insulating layer, in which the polysilicon is first applied as a continuous nearly amorphous silicon layer. This layer is thermally processed to promote the epitaxial growth of additional polycrystalline silicon thereon.
It is considered that none of the known prior art teaches a method in which a crystalline polysilicon deposit has a controlled crystal size varying with depth.